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t8502 and t8503 dual pcm codecs with filters document id# 080995 date: nov 01, 2002 rev: a version: 1 distribution: public features +5 v only two independent channels pin-selectable receive gain control pin-selectable -law or a-law companding automatic powerdown mode low-power, latch-up-free cmos technology ? 40 mw/channel typical operating power dissipation ? 12.5 mw/channel typical standby power dissipation automatic master clock frequency selection ? 2.048 mhz or 4.096 mhz independent transmit and receive frame strobes 2.048 mhz or 4.096 mhz data rate on-chip sample and hold, autozero, and precision volt- age reference differential architecture for high noise immunity and power supply rejection meets or exceeds itu-t g.711?g.712 requirements and vf characteristics of d3/d4 (as per bellcore pub43801) operating temperature range: ?40 c to +85 c description the t8502 and t8503 devices are single-chip, two- channel, -law/a-law pcm codecs with filters. these integrated circuits provide analog-to-digital and digital-to- analog conversion. they provide the transmit and receive filtering necessary to interface a voice telephone circuit to a time-division multiplexed system. these devices are packaged in both 20-pin sojs and 20-pin sogs. the t8502 differs from the t8503 in its timing mode. the t8502 operates in the delayed timing mode (digital data is valid one clock cycle after frame sync goes high), and the t8503 operates in the nondelayed timing mode (digital data valid when frame sync goes high) (see figures 5 and 6). figure 1. block diagram 5-3579 (f).b fs x 0 fs r 0 fs x 1 fs r 1 gndd gs x 0 vf x in0 vf r o0 gs x 1 vf x in1 vf r o1 ? + filter network encoder channel 0 +2.4 v decoder pcm interface gain control internal timing & control bias circuitry & reference channel 1 filter network d x d r mclk asel v dd gnda (2) gs0 gs1
2 2 t8502 and t8503 dual pcm codecs with filters functional description two channels of pcm data input and output are passed through only two ports, d x and d r , so some type of time- slot assignment is necessary. the scheme used here is to uti- lize a fixed-data rate mode of 32 or 64 time slots correspond- ing to master clock frequencies of either 2.048 mhz or 4.096 mhz, respectively. each device has four frame sync (fs x and fs r ) inputs, one pair for each channel. during a single 125 s frame, each frame sync input is supplied a single pulse. the timing of the respective frame sync pulse indi- cates the beginning of the time slot during which the data for that channel is clocked in or out of the device. fs x and fs r must be high for a minimum of one master clock cycle. they can be operated independently, or they can be tied together for coincident transmit and receive data transfer. during a frame, channel 0 and 1 transmit frame sync pulses must be separated from each other by one or more time slots. like- wise, channel 0 and 1 receive frame sync pulses must be sep- arated from each other by one or more time slots. both transmit and receive frame strobes must be derived from master clock, but they do not need to be byte aligned. a channel is placed in standby mode by removing both fs x and fs r for 500 s. note, if any one of those pulses (per channel) is removed, operation is indeterminate. standby mode reduces overall device power consumption by turning off nonessential circuitry. critical circuits that ensure a fast, quiet powerup are kept active. master clock need not be active when both channels are in standby mode. the frequency of the master clock must be either 2.048 mhz or 4.096 mhz. internal circuitry determines the master clock frequency during the powerup reset interval. the analog input section in figure 2 includes an on-chip op amp that is used in conjunction with external, user-supplied resistors to vary encoder passband gain. the feedback resis- tance (rf) should range from 10 k? to 200 k?, and capaci- tance from gs x to ground should be kept to less than 50 pf. the input signal at vf x in should be ac coupled. for best performance, the maximum gain of this op amp should be limited to 20 db or less. gain in the receive path is selectable via the gs pins as either 0 db or ?3.5 db. figure 2. typical analog input section pin information figure 3. pin diagram vf x in to 2.4 v gs x r i r f ? + codec filters gain = r f r i c i 5-3786 (f).a 5-3788 (f).b vf x in0 gs x 0 gnda0 vf r o0 gs0 v dd fs r 0 fs x 0 mclk gndd vf x in1 gs x 1 gnda1 vf r o1 gs1 asel fs r 1 fs x 1 d r d x 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 t-8502 t-8503
3 t8502 and t8503 dual pcm codecs with filters pin information (continued) * i d indicates a pull-down device is included on this lead. i u indicates a pull-up device is included on this lead. table 1. pin descriptions symbol pin type * name/function vf x in1 vf x in0 20 1 i voice frequency transmitter input. analog inverting input to the uncommitted operational amplifier at the transmit filter input. connect the signal to be digitized to this pin through a re- sistor r i (see figure 2). gs x 1 gs x 0 19 2 o gain set for transmitter. output of the transmit uncommitted operational amplifier. the pin is the input to the transmit differential filters. connect the pin to its corresponding vf x in through a resistor r f (see figure 2). vf r o1 vf r o0 17 4 o voice frequency receiver output. this pin can drive 2000 ? (or greater) loads. v dd 6 ? +5 v power supply . this pin should be bypassed to ground with at least 0.1 f of capacitance as close to the device as possible. gnda1 gnda0 18 3 ? analog grounds . all ground pins must be connected on the circuit board. d r 12 i receive pcm data input . the data on this pin is shifted into the device on the falling edges of mclk. data is only entered for valid time slots as defined by the fs r inputs. d x 11 o transmit pcm data output . this pin remains in the high-impedance state except during active transmit time slots. an active transmit time slot is defined as one in which a pulse is present on one of the fs x inputs. data is shifted out on the rising edge of mclk. mclk 9 i master clock input . the frequency must be 2.048 mhz or 4.096 mhz. this clock serves as the bit clock for all pcm data transfer. gndd 10 ? digital ground . ground connection for the digital circuitry. all ground pins must be connected on the circuit board. fs x 1 fs x 0 13 8 i d transmit frame sync . this signal is an edge trigger and must be high for a minimum of one mclk cycle. this signal must be derived from mclk. the division ratio is 1:256 or 1:512 (fs x :mclk). each fs x input must have a pulse present at the start of the desired active output time slot. pulses on fs x inputs must be separated by one or more integer multiples of time slots. if the device is to be used as an a/d converter only, fs x must be tied to fs r . an internal pull-down device is included on each fs x . fs r 1 fs r 0 14 7 i d receive frame sync . this signal is an edge trigger and must be high for a minimum of one mclk cycle. this signal must be derived from mclk. the division ratio is 1:256 or 1:512 (fs r :mclk). each fs r input must have a pulse present at the start of the desired active input time slot. pulses on fs r inputs must be separated by one or more integer multiples of time slots. if the device is to be used as a d/a converter only, fs r must be tied to fs x . an internal pull-down device is included on each fs r . gs1 gs0 16 5 i u gain selection . a high or floating state sets the receive path gain at 0 db; a logic low sets the gain to ?3.5 db. a pull-up device is included. asel 15 i d a-law/-law select . a logic low selects -law coding. a logic high selects a-law coding. a pull-down device is included.
4 t8502 and t8503 dual pcm codecs with filters absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in th e operational sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (esd) during handling and mounting. legerity employs a human-body model (hbm) and a charged- device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used to define the model. no industry-wide standard has been adopted for cdm. however, a standard hbm (resistance = 1500 ?, capacitance = 100 pf) is widely used and, therefore, can be used for comparison purposes. the hbm esd threshold presented here was obtained by using these circuit parameters: electrical characteristics specifications apply for t a = ?40 c to +85 c, v dd = 5 v 5%, mclk = either 2.048 mhz or 4.096 mhz, and gnd = 0 v, unless otherwise noted. dc characteristics table 2. digital interface parameter symbol min max unit storage temperature range t stg ?55 150 c power supply voltage v dd ? 6.5 v voltage on any pin with respect to ground ? ?0.5 0.5 + v dd v maximum power dissipation (package limit) p d ? 600 mw hbm esd threshold voltage device rating t8502 >2000 t8503 >2000 parameter symbol test conditions min typ max unit input low voltage v il all digital inputs ? ? 0.8 v input high voltage v ih all digital inputs 2.0 ? ? v output low voltage v ol d x , i l = 3.2 ma ? ? 0.4 v output high voltage v oh d x , i l = ?3.2 ma 2.4 ? ? v d x , i l = ?320 a 3.5 ? ? v input current, pins 9, 12 i i gndd < v in < v dd ?10 ? 10 a input current, pins 7, 8, 13, 14, 15 i i gndd < v in < v dd 2 ? 150 a input current, pins 5, 16 i i gndd < v in < v dd ?120 ? ?2 a output current in high-impedance state i oz d x ?30 <2 30 a input capacitance c i ? ? ? 5 pf
5 t8502 and t8503 dual pcm codecs with filters electrical characteristics (continued) dc characteristics (continued) table 3. power dissipation power measurements are made at mclk = 4.096 mhz with outputs unloaded and asel and gs[1:0] not connected. clock and frame sync levels are +5 v and 0 v. transmission characteristics table 4. analog interface channels operational parameter symbol test conditions min typ max unit 0 standby current i dds mclk present; fs x [1:0] = fs r [1:0] = 0 v ? 5 8 ma 1 partial standby current i ddp mclk present; fs pulses present for one channel, fs x = fs r = 0 v for other channel ? 10 16 ma 2 powerup current i dd1 mclk, fs pulses present ? 16 23 ma parameter symbol test conditions min typ max unit input resistance, vf x in r vf x i 0.25 v < vf x i < 4.75 v 1.0 60 ? m? input leakage current, vf x in i bvf x i 0.25 v < vf x i < 4.75 v ? 0.04 2.4 a dc open-loop voltage gain, gs x a vol ? 5000 ? ? ? open-loop unity gain bandwidth, gs x f o ? 1 3 ? mhz load capacitance, gs x cl x1 ? ? ? 50 pf load resistance, gs x rl x1 ? 10 ? ? k? input voltage, vf x in v ix relative to ground 2.25 2.35 2.5 v load resistance, vf r o rl vf r o ? 2000 ? ? ? load capacitance, vf r o cl vf r o ? ? ? 100 pf output resistance, vf r o ro vf r o 0 dbm0, 1020 hz pcm code applied to d r ? ? 20 ? standby mode fs x = fs r = 0 v for channel under test 3000 ? 10000 ? output voltage, vf r o v or alternating zero -law pcm code applied to d r 2.25 2.38 2.5 v output voltage, vf r o, standby vo rpd standby mode fs x = fs r = 0 v for channel under test, no load 2.0 2.35 2.65 v output voltage swing, vf r o v swr rl = 2000 ? 3.2 ? ? vp-p
6 t8502 and t8503 dual pcm codecs with filters transmission characteristics (continued) ac transmission characteristics unless otherwise noted, the analog input is a 0 dbm0, 1020 hz sine wave; the input amplifier is set for unity gain. the digital input is a pcm bit stream equivalent to that obtained by passing a 0 dbm0, 1020 hz sine wave through an ideal encoder. the output level is sin(x)/x-corrected. table 5. absol ute gain table 6. gain tracking table 7. distortion parameter symbol test conditions min typ max unit encoder milliwatt response (transmit gain tolerance) emw signal input of 0.775 vrms, -law or a-law 0 c to 85 c ?0.20 ? 0.20 dbm0 ?40 c to +85 c ?0.25 ? 0.25 dbm0 decoder milliwatt response (receive gain tolerance) dmw measured relative to 0.775 vrms -law or a-law, pcm input of 0 dbm0 1020 hz, rl = 10 k? 0 c to 85 c ?0.20 ? 0.20 dbm0 ?40 c to +85 c ?0.25 ? 0.25 dbm0 relative decoder gain variation referenced to dmw rgr decoder gain at ?3.5 db (gs = 0) ?40 c to +85 c ?0.15 ? 0.15 db parameter symbol test conditions min typ max unit transmit gain tracking error sinusoidal input -law/a-law gt x +3 dbm0 to ?37 dbm0 ?37 dbm0 to ?50 dbm0 ?0.25 ?0.50 ? ? 0.25 0.50 db db receive gain tracking error sinusoidal input -law/a-law gt r +3 dbm0 to ?37 dbm0 ?37 dbm0 to ?50 dbm0 ?0.25 ?0.50 ? ? 0.25 0.50 db db parameter symbol test conditions min typ max unit transmit signal to distortion sd x -law 3 dbm0 vf x i ?30 dbm0 a-law 3 dbm0 vf x i ?30 dbm0 36 35 ? ? ? ? db db -law ?30 dbm0 vf x i ?40 dbm0 a-law ?30 dbm0 vf x i v ?40 dbm0 30 29 ? ? ? ? db db -law ?40 dbm0 vf x i ?45 dbm0 a-law ?40 dbm0 vf x i ?45 dbm0 25 25 ? ? ? ? db db receive signal to distortion sd r -law 3 dbm0 vf r o ?30 dbm0 a-law 3 dbm0 vf r o ?30 dbm0 36 35 ? ? ? ? db db -law ?30 dbm0 vf r o ?40 dbm0 a-law ?30 dbm0 vf r o ?40 dbm0 30 29 ? ? ? ? db db -law ?40 dbm0 vf r o ?45 dbm0 a-law ?40 dbm0 vf r o ?45 dbm0 25 25 ? ? ? ? db db single frequency distortion, transmit sfd x 200 hz?3400 hz, 0 dbm0 input, output any other single frequency 3400 hz ? ? ?38 dbm0 single frequency distortion, re- ceive sfd r 200 hz?3400 hz, 0 dbm0 input, output any other single frequency 3400 hz ? ? ?40 dbm0 intermodulation distortion imd transmit or receive, two frequencies in the range (300 hz?3400 hz) at ?6 dbm0 ? ? ?42 dbm0
7 t8502 and t8503 dual pcm codecs with filters transmission characteristics (continued) ac transmission characteristics (continued) overload compression figure 4 shows the region of operation for encoder signal levels above the reference input power (0 dbm0). figure 4. overload compression table 8. envelope delay distortion parameter symbol test conditions min typ max unit t x delay, absolute d xa f = 1600 hz ? 280 300 s t x delay, relative to 1600 hz d xr f = 500 hz?600 hz f = 600 hz?800 hz f = 800 hz?1000 hz f = 1000 hz?1600 hz f = 1600 hz?2600 hz f = 2600 hz?2800 hz f = 2800 hz?3000 hz ? ? ? ? ? ? ? ? ? ? ? ? ? ? 220 145 75 40 75 105 155 s s s s s s s r x delay, absolute d ra f = 1600 hz ? 190 200 s r x delay, relative to 1600 hz d rr f = 500 hz?1000 hz f = 1000 hz?1600 hz f = 1600 hz?2600 hz f = 2600 hz?2800 hz f = 2800 hz?3000 hz ?40 ?30 ? ? ? ? ? ? ? ? ? ? 90 125 175 s s s s s round-trip delay, absolute d rta any time slot/channel to any time slot/channel f = 1600 hz ? 470 600 s 5-3586 (f) 1 2 3 4 5 6 7 8 9 123456789 acceptable region fundamental input power (dbm) fundamental output power (dbm)
8 t8502 and t8503 dual pcm codecs with filters transmission characteristics (continued) ac transmission characteristics (continued) table 9. noise table 10. receive gain relative to gain at 1.02 khz table 11. transmit gain relative to gain at 1.02 khz parameter symbol test conditions min typ max unit transmit noise, -law n xc ? ? ? 18 dbrnc0 input amplifier gain = 20 db ? ? 19 dbrnc0 transmit noise, a-law n xp ? ? ? ?68 dbm0p receive noise, -law n rc pcm code is alternating positive and negative zero ? ? 13 dbrnc0 receive noise, a-law n rp pcm code is a-law positive one ? ? ?75 dbm0p noise, single frequency, f = 0 khz?100 khz n rs vf x in = 0 vrms, measurement at vf r o, d r = d x ? ? ?53 dbm0 power supply rejection transmit psr x v dd = 5.0 vdc + 100 mvrms: f = 0 khz?4 khz f = 4 khz?50 khz 36 30 ? ? ? ? db db power supply rejection receive psr x pcm code is positive one lsb v dd = 5.0 vdc + 100 mvrms: f = 0 khz?4 khz f = 4 khz?25 khz f = 25 khz?50 khz 36 40 30 ? ? ? ? ? ? db db db spurious out-of-band signals at vf r o relative to input sos 0 dbm0, 300 hz?3400 hz input pcm code applied: 4600 hz?7600 hz 7600 hz?8400 hz 8400 hz?50 khz ? ? ? ? ? ? ?30 ?40 ?30 db db db frequency (hz) min typ max unit below 3000 ?0.150 0.04 0.150 db 3140 ?0.570 0.04 0.150 db 3380 ?0.735 ?0.58 0.010 db 3860 ? ?10.7 ?9.4 db 4600 and above ? ? ?28 db frequency (hz) min typ max unit 16.67 ? ?35 ?30 db 40 ? ?34 ?26 db 50 ? ?36 ?30 db 60 ? ?50 ?30 db 200 ?1.8 ?0.5 0 db 300 to 3000 ?0.150 0.04 0.150 db 3140 ?0.570 0.04 0.150 db 3380 ?0.735 ?0.58 0.010 db 3860 ? ?10.7 ?9.4 db 4600 and above ? ? ?32 db
9 t8502 and t8503 dual pcm codecs with filters transmission characteristics (continued) ac transmission characteristics (continued) table 12. interchannel crosstalk (between channels) r f = 200 k? (see note.) table 13. intrachannel crosstalk (within channels) r f = 200 k? (see note.) note: for tables 12 and 13, crosstalk into the transmit channels (vf x in) can be significantly affected by parasitic capacitive feeds from gs x and vf r o outputs. pwb layouts should be arranged to keep these parasitics low. the resistor value of r f (from gs x to vf x in) should also be kept as low as possible (while maintaining the load on gs x above 10 k?, per table 4) to minimize crosstalk. parameter symbol test conditions min typ max unit transmit to receive crosstalk 0 dbm0 transmit levels ct xx-ry f = 300 hz?3400 hz idle pcm code for channel under test; 0 dbm0 into other channel vf x in ? ?100 ?77 db receive to transmit crosstalk 0 dbm0 receive levels ct rx-xy f = 300 hz?3400 hz vf x in = 0 vrms for channel under test; 0 dbm0 code level on other channel d r ? ?92 ?77 db transmit to transmit crosstalk 0 dbm0 transmit levels ct xx-xy f = 300 hz?3400 hz vf x in = 0 vrms for channel under test; 0 dbm0 into other channel vf x in ? ?90 ?77 db receive to receive crosstalk 0 dbm0 receive levels ct rx-ry f = 300 hz?3400 hz idle pcm code for channel under test; 0 dbm0 code level on other channel d r ? ?102 ?77 db parameter symbol test conditions min typ max unit transmit to receive crosstalk 0 dbm0 transmit levels ct xx-rx f = 300 hz?3400 hz idle pcm code for channel under test; 0 dbm0 into vf x in ? ?80 ?70 db receive to transmit crosstalk 0 dbm0 receive levels ct rx-xx f = 300 hz?3400 hz vf x in = 0 vrms for channel under test; 0 dbm0 code level on d r ? ?88 ?70 db
10 t8502 and t8503 dual pcm codecs with filters timing characteristics table 14. clock section (see figures 5 and 6.) table 15. t8502 transmit section (see figure 5.) * timing parameter tmcldz is referenced to a high-impedance state. table 16. t8503 transmit section (see figure 6.) * timing parameter tmchdz is referenced to a high-impedance state. table 17. t8502 and t8503 receive section (see figures 5 and 6.) symbol parameter test conditions min typ max unit tmchmcl1 clock pulse width ? 97 ? ? ns tmch1mch2 tmcl2mcl1 clock rise and fall time ? 0 ? 15 ns symbol parameter test conditions min typ max unit tmchdv data enabled on ts entry 0 < c load < 100 pf 0 ? 60 ns tmchdv1 data delay from mc 0 < c load < 100 pf 0 ? 60 ns tmcldz* data float on ts exit c load = 0 10 ? 100 ns tfshmcl frame-sync hold time ? 50 ? ? ns tmclfsh frame-sync high setup ? 50 ? ? ns tfslmcl frame-sync low setup ? 50 ? ? ns tfshfsl frame-sync pulse width ? 0.1 ? 125 ? tmchmch s symbol parameter test conditions min typ max unit tfshdv data enabled on ts entry 0 < c load < 100 pf 0 ? 80 ns tmchdv1 data delay from fs x 0 < c load < 100 pf 0 ? 60 ns tmchdz* data float on ts exit c load = 0 0 ? 30 ns tfshmcl frame-sync hold time ? 50 ? ? ns tmclfsh frame-sync high setup ? 50 ? ? ns tfslmcl frame-sync low setup ? 50 ? ? ns tfshfsl frame-sync pulse width ? 0.1 ? 125 ? tmchmch s symbol parameter test conditions min typ max unit tdvmcl receive data setup ? 30 ? ? ns tmcldv receive data hold ? 15 ? ? ns
11 t8502 and t8503 dual pcm codecs with filters timing characteristics (continued) note: fs x and fs r do not need to be coincident. figure 5. t8502 transmit and receive timing note: fs x and fs r do not need to be coincident. figure 6. t8503 transmit and receive timing 5-3581 (c).i 5-3581 (c).r
12 t8502 and t8503 dual pcm codecs with filters applications figure 7. typical t8502 and t8503/slic interconnection 5-3584 (f).b slic t8502 t8503 vf r on acin vf x inn v tr gs x n zhb zt1 zrcv zt2 0.1f 0.1f rf rg
13 t8502 and t8503 dual pcm codecs with filters outline diagrams 20-pin soj dimensions are in millimeters. number of pins (n) maximum length (l) maximum width without leads (b) maximum width including leads (w) maximum height above board (h) 20 12.95 7.62 8.81 3.18 n 1 pin #1 identifier zone 0.51 max 0.79 max 0.10 seating plane 1.27 typ h w b l 5-4413 (f).r4
14 t8502 and t8503 dual pcm codecs with filters outline diagrams (continued) 20-pin sog dimensions are in millimeters. number of pins (n) maximum length (l) maximum width without leads (b) maximum width including leads (w) maximum height above board (h) 20 13.00 7.62 10.64 2.67 5-4414 (c)r.4 n 1 pin #1 identifier zone 0.51 max 0.28 max 0.10 seating plane 1.27 typ h w b l 0.51 max 0.61
15 t8502 and t8503 dual pcm codecs with filters ordering information note: all parts are shipped in dry bag. device part no. package temperature comcode t-8502 - - el2-d 20-pin soj ?40 c to +85 c 108295908 t-8502 - - el2-dt 20-pin soj tape & reel ?40 c to +85 c 108295916 t-8502 - - gl2-d 20-pin sog ?40 c to +85 c 108295924 t-8502 - - gl2-dt 20-pin sog tape & reel ?40 c to +85 c 108295932 t-8503 - - el2-d 20-pin soj ?40 c to +85 c 108295940 t-8503 - - el2-dt 20-pin soj tape & reel ?40 c to +85 c 108295957 t-8503 - - gl2-d 20-pin sog ?40 c to +85 c 108295965 t-8503 - - gl2-dt 20-pin sog tape & reel ?40 c to +85 c 108295973
legerity, inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liabilit y is assumed as a result of their use or application. copyright ? 2002 legerity, inc. all rights reserved
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